Field of the Invention
The present invention relates to a thin film transistor (TFT) and a method for manufacturing the same and more particularly to the TFT using a polycrystalline semiconductor thin film formed on an insulating substrate as an active layer and to the method for manufacturing the TFT.
The present application claims priority of Japanese Patent Application No. 2003-067858 filed on Mar. 13, 2003, which is hereby incorporated by reference.
Description of the Related Art
Silicon is widely used as a semiconductor material for manufacturing a semiconductor device typified by an LSI (Large Scale Integrated) circuit. A TFT using a silicon thin film other than a single crystal silicon, such as an amorphous silicon thin film, a polycrystalline silicon thin film and a like, as an active layer, is used in a liquid crystal display (LCD), a contact-type image sensor, and a like. For example, in an active-matrix-type LCD, a TFT for a pixel being connected to a liquid crystal pixel placed in a matrix form is employed. Such the TFT has a MOS (Metal Oxide Semiconductor)-type structure in which an amorphous silicon thin film deposited at temperatures being lower than those employed when a single crystal silicon is deposited, or a polycrystalline silicon is deposited on a transparent insulating substrate such as a glass substrate (hereinafter may referred simply to as an “insulating substrate”), and a source region and a drain region are formed by implanting an impurity using an ion doping method.
An amorphous silicon thin film, as described above, has an advantage in that it can be deposited at relatively low temperatures, which enables the TFT to be manufactured by using, as the insulating substrate, a low-priced glass substrate having low heat resistance and in that it is excellent in mass productivity. Therefore, such the amorphous silicon thin film is widely used in LCDs, or a like. However, the amorphous silicon thin film has a disadvantage. That is, since the amorphous silicon thin film has no crystalline property, which causes its crystal grain to be small, it provides low carrier mobility. Therefore, if a driving TFT used in a driving circuit of an LCD is manufactured using such the amorphous silicon thin film at the same time when the TFT to be used for a pixel as above is manufactured, driving capability and operation speed of the driving circuit become low. Because of this, in an LCD using an amorphous silicon thin film as a TFT for a pixel, in many cases, a driving TFT in the driving circuit is employed in a form of an externally mounted component. In recent years, however, in an LCD, a need for being made thin and small-sized is increasing due to diversity of its applications and, as a result, a connecting pitch between the LCD and driving circuit on an insulating substrate becomes narrow and small. Therefore, if the driving circuit uses a driving TFT in a form of an externally mounted component, constraints are added when the connecting pitch has to be made narrow and small, which makes it difficult to achieve a large-screen and high-definition LCD.
On the other hand, in an TFT using a polycrystalline silicon thin film, instead of an amorphous silicon thin film, the polycrystalline silicon thin film, since it has a crystalline property to some extent, which causes its crystal grain to be larger than that of the amorphous silicon thin film, provides carrier mobility being higher than that of the amorphous silicon thin film. Therefore, in an LCD using a polycrystalline silicon thin film as a pixel TFT, by manufacturing a driving TFT using the polycrystalline silicon thin film at the same time when the pixel TFT is manufactured, driving capability and operation speed of a driving circuit can be improved. Moreover, the driving TFT and pixel TFT can be integrally formed on an insulating substrate, a connecting pitch between an LCD and driving circuit can be made narrow and small, thus enabling the LCD to be made thin and small sized. Therefore, a TFT using a polycrystalline silicon thin film tends to be preferably employed.
To form such the polycrystalline silicon thin film as described above, generally, after having deposited, in advance, an amorphous silicon thin film on an insulating substrate by a P-CVD (Plasma Chemical Vapor Deposition) method, by crystallizing the amorphous silicon thin film by performing heat treatment using a laser annealing method or a like, the amorphous silicon thin film is changed to be a polycrystalline silicon thin film. It is conventionally known that, after a source region and a drain region by using the polycrystalline silicon thin film obtained by the above method have been formed, when a TFT is manufactured by forming a gate electrode with a gate insulating film made up of a silicon dioxide (SiO2) film being interposed between the gate electrode and the source region and drain region, an orbit in a nonbonded state called “dangling bond” in a polycrystalline silicon occurs at an interface between the polycrystalline silicon thin film serving as an active layer and the silicon dioxide (SiO2) film serving as the gate insulating film. Since the dangling bond acts as a factor that increases a trap density in a grain boundary in the polycrystalline silicon, carrier mobility of the polycrystalline silicon becomes low and an increase in a threshold voltage or a like occurs, which produces a problem that a characteristic of a transistor is degraded.
Therefore, a method of hydrogenating the dangling bond is conventionally employed in which, by feeding hydrogen to the dangling bond and diffusing hydrogen into the dangling bond, an orbit being in a nonbonded state for a polycrystalline silicon is bonded to a hydrogen atom for being terminated. More concretely, in the hydrogenation of the dangling bond, by performing heat treatment, after having formed, in advance, a hydrogen feeding layer containing, hydrogen, within a part of a TFT, or by performing heat treatment in an atmosphere containing hydrogen, hydrogen is made to be diffused into the dangling bond.
A TFT in which such a hydrogen feeding layer for hydrogenation as described above is formed is disclosed in, for example, in Japanese Patent Application Laid-open No. Hei 6-77484 (first conventional example). The disclosed TFT 100, as shown in FIG. 9, includes an insulating substrate 101 made up of a glass substrate, a polycrystalline silicon thin film 102 formed on the insulating substrate 101, a source region 103 formed on one end of the polycrystalline silicon thin film 102, a drain region 104 formed on the other end of the polycrystalline silicon thin film 102, a channel region 105 formed between the source region 103 and drain region 104, a gate insulating film 106 made up of a silicon dioxide film formed on the polycrystalline silicon region 102, and a gate electrode 107 formed on the gate insulating film 106.
The disclosed TFT 100, as shown in FIG. 9, further includes an interlayer dielectric 108 made up of a silicon dioxide film formed on an entire surfaces being exposed containing a surface of the gate electrode 107, contact holes 109A and 109B formed in the interlayer dielectric 108, a source electrode 110 made up of an aluminum film formed so as to be connected to the source region 103, a drain electrode 111 made up of an aluminum film formed so as to be connected to the drain region 104, and a passivation film 112 made up of silicon nitride (Si3N4) containing much hydrogen on entire surfaces being exposed including surfaces of the source electrode 110 and the drain electrode 111. At a last stage of the TFT forming process, the hydrogenation is achieved by performing heat treatment, at 300° C. to 450° C., on the passivation film 112 serving as the hydrogen feeding layer to diffuse hydrogen contained in the hydrogen feeding layer in the dangling bond at an interface between the polycrystalline silicon thin film 102 and the gate insulating film 106.
However, in the conventional TFT 100 shown in FIG. 9, since the passivation film 112 is placed away by 1 μm from an interface between the polycrystalline silicon thin film 102 used to diffuse hydrogen and the gate insulating film 106, a diffusing distance of hydrogen is made long. Therefore, since much time is required in the heat treatment to sufficiently perform the hydrogenation process, there is a fear that a TFT is affected thermally. In the case of the TFT being large in size in particular, the influence is large.
To solve this problem, another TFT (second conventional example) in which a hydrogenation process is sufficiently performed by shortening a diffusing distance of hydrogen is disclosed also, as another example, in the above same Japanese Patent Application Laid-open No. Hei 6-77484. The disclosed TFT 120, as shown in FIG. 10, includes a lower layer polycrystalline thin film 121 formed on an insulating substrate 101, a hydrogen feeding layer 122 containing much hydrogen made up of a silicon nitride film and formed on the lower layer polycrystalline thin film 121, and an upper layer polycrystalline thin film 123, serving as an active layer, formed on the hydrogen feeding layer 122 in a manner to confine the hydrogen feeding layer 122. Moreover, same reference numbers are assigned to components having the same functions as those shown in FIG. 9 and descriptions of them are omitted accordingly.
According to the TFT 120 of the second conventional example as described above, the hydrogen feeding layer 122 is formed directly below the upper polycrystalline thin film 123 serving as the active layer and, therefore, the hydrogen feeding layer 122 is placed close to the interface between the upper polycrystalline silicon thin film 123 to be used for diffusing hydrogen and the gate insulating film 106, which enables the diffusing distance of hydrogen to be shortened. As a result, a sufficient hydrogenation process can be performed without much time being taken in the heat treatment.
Next, main processes of manufacturing the TFT 120 of the second conventional example are explained by referring to FIGS. 11A to 11E. First, as shown in FIG. 11A, after having deposited an amorphous silicon thin film on the insulating substrate 101 by using a P-CVD method, by applying a laser beam, for example, such as an exima laser to the amorphous silicon thin film to crystallize the amorphous silicon thin film so that it is changed to be a lower polycrystalline thin film 121. Then, as shown in FIG. 11B, the hydrogen feeding layer 122 is formed on the lower polycrystalline silicon thin film 121 made up of a silicon nitride film containing much hydrogen by using the P-CVD method. Next, as shown in FIG. 11C, patterning is performed by a photolithography method on the hydrogen feeding layer 122 so as to have a desired shape.
Then, as shown in FIG. 11D, the upper polycrystalline silicon thin film 123 is deposited on entire surfaces being exposed including a surface of the hydrogen feeding layer by the same method as employed when the lower polycrystalline silicon thin film 121 is deposited. Next, as shown in FIG. 1E, patterning is performed by the photolithography method on the lower polycrystalline silicon thin film 121 and the upper polycrystalline silicon film 123 at the same time so as to have a desired shape. Thus, the structure as shown in FIG. 10 is obtained in which the hydrogen feeding layer 122 is confined between the lower polycrystalline thin film 121 and upper polycrystalline thin film 123. By employing such the method of manufacturing the TFT as described above, it is made possible to manufacture the TFT as shown in FIG. 10 in which the hydrogen feeding layer 122 is placed close to the interface between the polycrystalline silicon thin film 123 used to diffuse hydrogen and the gate insulating film 106.
However, the conventional TFT and conventional method for manufacturing the same disclosed in Japanese Patent Application Laid-open No. Hei 6-77484 described above have a problem in that, in the disclosed technology, the photolithography process required to form the hydrogen feeding layer are increased, which causes a rise in manufacturing costs. That is, as described above, to manufacture the conventional TFT 20 as shown in FIG. 10, by using the manufacturing processes shown in FIGS. 11A to 11E, the structure has to be formed in which the hydrogen feeding layer 122 is confined between the lower polycrystalline silicon thin film 121 and the upper polycrystalline silicon thin film 123. However, as shown in FIG. 11C, to perform patterning on the hydrogen feeding layer 122 so as to have a desired shape, it is necessary to use additional photolithography processes. Moreover, in order to confine the hydrogen feeding layer 122, in addition to the upper polycrystalline silicon thin film 123 serving as the active layer, the lower polycrystalline silicon thin film 121 has to be deposited, which requires additional P-CVD processes. Such the increase in manufacturing processes causes reduction in yields, thus causing a rise in costs of manufacturing TFTs.